Aims and Objectives
Accelerators have become an important component of modern supercomputer architectures. In recent years, the diversity with respect to accelerator architectures has increased. Additionally, the utilization of specialized hardware can ensure performance increases in a world where traditional mechanisms of performance gains such as Moore’s law seem to slow down. This can make it attractive to potentially even utilize multiple types of processors or accelerators within a single application, if different tasks within that application exhibit different characteristics that are best exploited by varying types of processors.
As a result, portable programming models are required that are able to target multiple types of devices simultaneously, while at the same time shielding the users from the complexities of programming such complex system architectures.
To address these issues, the hipSYCL project provides a modern implementation of the Khronos SYCL programming model with multiple backends that cover a wide range of currently available hardware. Additionally, hipSYCL serves as a research platform for programming model development, as well as compiler and parallel runtime technologies.
The development of hipSYCL is supported by Intel within the framework of a oneAPI Center of Excellence.
Within the hipSYCL project, we are interested in heterogeneous and hardware-aware computing from multiple angles:
Improving the expressiveness and power of the SYCL programming model in general to allow users to extract more performance with less code;
Performance optimizations using modern compiler and runtime technologies for heterogeneous computing in order to develop a SYCL implementation that delivers excellent performance for existing SYCL code;
Developing advanced scheduling mechanisms to efficiently distribute work across processors within a heterogeneous system, including performance models of kernel runtime and similar techniques to assist scheduling decisions.
People from EMCL
Talk: Aksel Alpay and Vincent Heuveline. 2020. SYCL beyond OpenCL: The architecture, current state and future direction of hipSYCL. In Proceedings of the International Workshop on OpenCL (IWOCL '20). Association for Computing Machinery, New York, NY, USA, Article 8, 1. DOI:https://doi.org/10.1145/3388333.3388658 (watch recording on YouTube)
Talk: Sohan Lal, Aksel Alpay, Philip Salzmann, Biagio Cosenza, Nicolai Stawinoga, Peter Thoman, Thomas Fahringer, and Vincent Heuveline. 2020. SYCL-Bench: A Versatile Single-Source Benchmark Suite for Heterogeneous Computing. In Proceedings of the International Workshop on OpenCL (IWOCL '20). Association for Computing Machinery, New York, NY, USA, Article 10, 1. DOI:https://doi.org/10.1145/3388333.3388669 (watch recording on YouTube)
Sohan Lal, Aksel Alpay, Philip Salzmann, Biagio Cosenza, Alexander Hirsch, Nicolai Stawinoga, Peter Thoman, Thomas Fahringer, Vincent Heuveline. 2020. SYCL-Bench: A Versatile Cross-Platform Benchmark Suite for Heterogeneous Computing. In: Malawski M., Rzadca K. (eds) Euro-Par 2020: Parallel Processing. Euro-Par 2020. Lecture Notes in Computer Science, vol 12247. Springer, Cham. https://doi.org/10.1007/978-3-030-57675-2_39