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Data Flow Computing on FPGAs using MaxCompiler from Maxeler Technologies


Despite the tremendous increase of compute power, the use of modern multi- and/or many-core architectures is challenging in the context of high performance computing.  One reason is the energy wall related to the increasing CPU clock frequencies which lead to untractable costs for energy. In order to cope with these challenges - also considering the constraints towards scalability - the FPGA technology opens new doors that can be considered for numerical simulation. One key issue is related to the ability to reconfigure the underlying hardware for a given application. This hardware reconfigurability leads to a paradigm shift where both the software and the hardware can be adapted in a synergetic way.

For numerical simulation a main drawback of using an FPGA is the tedious development cycles based on VHDL or Verilog. In this project we consider the use of a new compiler technology from the company Maxeler Technologies, which allows to program and reconfigure an FPGA by means of a higher level language like JAVA. It is then possible to benefit from the advantages of data flow computing without having to cope with the complex and time-consuming hardware language VHDL.

Research Focus

The focus is on analyzing the efficiency of numerical algorithms using data flow computing. The main topics are:

  • Implementing iterative solvers based on stencil computations on a MaxWorkstation using MaxCompiler
  • Optimization of the implemented algorithms to obtain the maximum speed-up while minimizing memory usage
  • Analysis of the potential for porting algorithms and the energy efficiency to be gained

Project Partners

  • Engineering Mathematics and Computing Lab (EMCL)
  • Institute of Computer Science and Engineering (ITEC@KIT)
  • Institute for Applied Computer Science (IAI@KIT)